1. Field of the Invention
The present invention generally relates to 3D chip assemblies, and more particularly to an anticipatory implant technique to reduce contamination during through-substrate via formation.
2. Background of Invention
Advancements in the area of semiconductor fabrication have enabled the manufacturing of integrated circuits that have a high density of electronic components. A challenge arises where an increase in the number and length of interconnect wirings can cause an increase in circuit resistance-capacitance delay and power consumption, which can negatively impact circuit performance. Three-dimensional (3D) stacking of integrated circuits can address these challenges. Fabrication of 3D integrated circuits includes at least two silicon wafers stacked vertically. Vertically stacked wafers can reduce interconnect wiring length and increase semiconductor device density. Deep through-substrate vias (TSVs) may be formed to provide interconnections and electrical connectivity between the electronic components of the 3D integrated circuits. Such TSVs may require high aspect ratios, where the via height is large with respect to the via width, to save valuable area in an integrated circuit design. Therefore, semiconductor device density can be increased and total length of interconnect wiring may be decreased by incorporating TSVs in 3D integrated circuits.
In order to form an electrical connection between the components of two wafers, stacked one on top of the other, a TSV may extend through the entire thickness of a single wafer. More specifically, a TSV may extend through multiple interconnect levels and through a semiconductor substrate (hereinafter “substrate”) in which semiconductor devices (hereinafter “devices”) may be formed. The interconnect levels may generally be located above the substrate, and may include multiple connections to and between the devices formed in the substrate.
A deep trench may typically be etched into the wafer through the interconnect levels and through the substrate in order to form the TSV. The devices formed in the substrate may be exposed to impurities as a result of etching through the interconnect levels. These impurities may diffuse into the substrate, and collect below the devices. More specifically, the impurities tend to migrate in dielectric materials, such as, for example a dielectric TSV liner or a buried oxide layer of a silicon-on-insulator substrate. A concentration of impurities below a device may affect the operational characteristics of that device, for example the threshold voltage. An unwanted change in the threshold voltage of a particular device may undermine the functionality of that device.
Accordingly, it may be advantageous to address the deficiencies described above.